Week 5: Exploring Verilog, Hardware Description Language

Welcome back, everyone! Last week, I explored the initial development of the robot path-finding algorithm. As I mentioned in my earlier blogs, I plan to implement this algorithm on FPGA.

This week, I will discuss my learning of Verilog, the hardware description language, and I’ll explain further detail about HDLs. A Hardware description language describes how digital hardware behaves in circuits. Digital hardware consists of combinational and sequential elements. A combinational circuit consists of digital elements whose output solely depends on its inputs. So, combinational circuits do not require memory, for example, AND, OR, NOT, NAND, NOR gates, multiplexers, encoders, decoders, etc. On the other hand, the output of a sequential circuit depends on its inputs and the previous state of its output. Sequential circuits must retain the last state of the output, meaning they implement some memory.

I explored how to model combinational and sequential circuits using Verilog. Overall, the robot path-finding algorithm can be divided into different states of the robot, its position at a given time, and the actions the robot would take in each of these states.

Verilog supports various behavioral modeling blocks. There are two main procedural blocks called “always” and “initial.” All statements in the “always” block execute until the inputs used in the blocks and listed in the sensitivity list have a change. In contrast, the “initial” block is executed only once in the simulation. Clearly, anything that works only once after the power is on has no equivalent digital circuit representation, and thus, the “initial” block is not synthesizable. But the “always” block represents the true behavior of the digital circuit and therefore is synthesizable to the netlist of digital elements. Both blocks can be modeled with a “begin-end” or a “fork-join” construct. All the statements within the “begin-end” construct execute sequentially unless there is a “non-blocking” assignment within those statements. “Non-blocking” assignments happen simultaneously, simulating the actual behavior of the typical digital circuit.

On the other hand, assignments in blocking statements happened sequentially. All the statements within the “fork-join” block execute simultaneously, irrespective of blocking or non-blocking assignments. “Fork-join” blocks are not synthesizable. Synthesized HDL code can generate a netlist of realizable digital elements called RTL (Register Transfer Level) code.

I learned that Verilog is a versatile language that can actually be used to create a wide range of circuits! For instance, ‘Case’ and ‘if’ statements can be used to design multiplexers, encoders, decoders, and priority encoders, among other combinational circuits. ‘Always’ blocks, when combined with a sensitivity list that includes ‘posedge’ (rising edge) or ‘negedge’ (falling edge) of the clock, can model flip flops or synchronous memory. Verilog also offers a variety of operators, including binary, unary, reduction, ternary, equality, concatenation, logical, and bitwise, which can be used to create complex circuit logic.

In fact, Verilog also supports a variety of loop control logic for behavioral modeling. “For” loops can model shift registers. “While” and “repeat” loops can effectively model the behavior of repetitive parts of the logic. “For” loops can be synthesizable if they have a known constant number of iterations.

That was a significant amount of technical background, which will help me implement my path-finding algorithm using a Finite State Machine and some combinational logic circuit logic. The Finite State Machine, a practical application of Verilog, uses the clocked version of the next state as the current state. The combination portion of the Finite State Machine is modeled using a ‘case’ statement, demonstrating the real-world application of Verilog in robotics.

Come back next week to find out how I have used these Verilog constructs to model the robot path-finding algorithm!